ABI Electronics · Boundary Scan Test & Programming
JTAGMaster Boundary Scan Tester
One IEEE 1149.1 boundary scan unit for in-circuit testing and programming of programmable logic devices
JTAGMaster is an integrated test and programming tool for programmable logic devices (PLDs). It reads and drives device pin states through the industry-standard IEEE 1149.1 boundary scan architecture and configures the devices over the same port. Automatic JTAG chain detection, automatic device learning, pin-to-pin comparison and EXTEST manual pin control let an engineer verify a board, program it and retest it with no physical probes. For labs and repair engineers it is a fast way to diagnose complex digital boards while keeping fixture costs down.
Overview
JTAGMaster is ABI Electronics' integrated test and programming tool for programmable logic devices. It uses the standard Test Access Port and boundary scan architecture (IEEE 1149.1) to read pin states, configure devices and diagnose faults. The accompanying software lets the user build test procedures freely and adds automatic learning of device states, pin-to-pin comparison and report generation. The internal device library is updated with BSDL files downloaded from the device manufacturers' websites. Beyond boundary scan, JTAGMaster programs from JAM STAPL and SVF files and, through an external adapter, programs EEPROMs over the SPI, I2C and Microwire serial protocols. The unit draws its power from the USB port, measures 83 x 52 x 16 mm and weighs 200g. It is CE approved and RoHS compliant, and a full training package is available to get new users productive quickly.
Key specifications
| Test architecture | IEEE 1149.1 (JTAG) boundary scan |
|---|---|
| Programming file formats | JAM STAPL, SVF |
| Serial protocols supported | SPI, I²C, Microwire (μwire) |
| Device description | BSDL (Boundary Scan Description Language) files |
| Operating voltage | 5V (USB powered) |
| Power consumption | 500mW |
| Dimensions | 83 x 52 x 16 mm |
| Weight | 200g |
| Operating temperature | 0°C to 50°C |
| Storage temperature | 0°C to 70°C |
| Humidity | Up to 80% non-condensing |
| Compliance | CE approved, RoHS compliant |
Features
Boundary scan testing
The IEEE 1149.1 boundary scan architecture observes each pin state individually, so complex digital boards can be verified without physical probes.
Multi-device programming
Programs from JAM STAPL and SVF files, and programs EEPROMs through an external adapter over the SPI, I2C and Microwire serial protocols.
Automatic chain detection and device learning
Detects the JTAG scan chain and learns device states automatically, then offers pin-to-pin comparison and reporting to speed up setup and diagnosis.
EXTEST manual pin control
EXTEST mode drives pin states by hand, so an engineer can build and verify custom test procedures.
Configurable software platform
ABI's software lets the user configure test procedures and instrument settings, with a Scan Check multi-license for several stations.
USB powered, light and small
Runs from 5V USB at only 500mW, weighs 200g, and is CE approved and RoHS compliant, so it travels easily for field use.
Typical applications
Manufacturing test
Solder defect detection on BGA and high-density assemblies
Modern boards rely on BGA packages whose joints sit under the device where no probe station or bed-of-nails fixture can reach. JTAGMaster gains access through the JTAG boundary scan chain and finds bridging shorts, opens and dry joints on the line. Whole-board interconnect verification is done without a large fixture, which lowers manufacturing cost and raises first-pass yield.
Firmware programming
On-board programming of FPGA, CPLD and Flash memory in production
At design release or in volume production, engineers use JTAGMaster for in-system programming (ISP) of FPGA, CPLD and Flash devices already soldered to the board, avoiding a costly stand-alone programmer and IC sockets. After shipment, a firmware update goes in through the same on-board JTAG connector with no board removal or device swap.
Repair and debug
Fault localization and repair verification on complex boards
Faced with a damaged or misbehaving board, the repair engineer builds an automated sequence in AIMs TestFlow that narrows the fault step by step down to a specific net or IC pin. With schematic and photo annotations in the flow, staff outside the OEM can follow the diagnosis in order, which reduces mean time to repair (MTTR).
Options and configuration
Tick the options you need. We compile the configuration into a list and carry it into the quote request form.
Standard equipment (included)
Hardware options
Software options
Downloads
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